vhd xlinix 뭔가 잘못되었습니다 muxes와 함께 있어야합니다 동일한 값을

Question

자일링스 vhd 내 프로그램에 문제가 있습니다. MIPS32 add, sub, and, lw, sw, 사인 및 코사인의 기본 지침을 지원하는 프로세서를 만들어야합니다. 사인과 코사인은 인수로 인수를 취해 각도의 코사인 또는 죄를 0에서 1000까지의 단일 정밀도 및 정수로 반환합니다. 16 진수 출력을 생성하는 Excel 파일이 있습니다 (Mips32 명령의 경우) 하나의 구성 요소 (InstructionRom에 있음)에서 사용하는 것 추가 할 입력 번호 또는 sub 및 ..etc.I 구성 요소 DataRam에 16 진수로 씁니다.

문제는 동일한 값을 가진 ReadData1과 ReadData2의 맨 위 구성 요소에 있습니다. 아래에는 2 개의 스크린 샷과 최상위 엔티티가 다른 구성 요소와 어떻게 연결되어 있습니까? 다른 구성 요소가 작동 중입니다. 누구든지 봐 주시겠습니까?

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

-- Uncomment the following library declaration if using 
-- arithmetic functions with Signed or Unsigned values 
--use IEEE.NUMERIC_STD.ALL; 

-- Uncomment the following library declaration if instantiating 
-- any Xilinx primitives in this code. 
--library UNISIM; 
--use UNISIM.VComponents.all; 

entity myTOP is 
    Port (clk : in STD_LOGIC; 
      reset : in STD_LOGIC; 
       instruction : out STD_LOGIC_VECTOR (31 downto 0); 
       regA : out STD_LOGIC_VECTOR (31 downto 0); 
       regB : out STD_LOGIC_VECTOR (31 downto 0); 
       ALUout : out STD_LOGIC_VECTOR (31 downto 0); 
       writeReg : out STD_LOGIC_VECTOR (4 downto 0); 
       Opcode : out STD_LOGIC_VECTOR (5 downto 0); 
       SinCos : out STD_LOGIC_VECTOR (31 downto 0); 
       DataOUT : out STD_LOGIC_VECTOR (31 downto 0); 
       ReadDATA1 : out STD_LOGIC_VECTOR (31 downto 0); 
      ReadDATA2 : out STD_LOGIC_VECTOR (31 downto 0); 
       WriteData : out STD_LOGIC_VECTOR (31 downto 0)); 
end myTOP; 

architecture Behavioral of myTOP is 

component InstructionsROM is 
    Port (InstructionAddress : in STD_LOGIC_VECTOR (9 downto 0); 
      Instruction : out STD_LOGIC_VECTOR (31 downto 0)); 
end component; 

component myPCRegister is 
    Port (PC_INPUT : in STD_LOGIC_VECTOR (9 downto 0); 
      PC_OUTPUT : out STD_LOGIC_VECTOR (9 downto 0); 
      clk : in STD_LOGIC; 
      RESET : in STD_LOGIC); 
end component; 

component my_10bitAdder is 
    Port (a : in STD_LOGIC_VECTOR (9 downto 0); 
      b : in STD_LOGIC; 
      cin : in STD_LOGIC; 
      cout : out STD_LOGIC; 
      z : out STD_LOGIC_VECTOR (9 downto 0)); 
end component; 


component my_5bitMUX is 
    Port (a : in STD_LOGIC_VECTOR (4 downto 0); 
      b : in STD_LOGIC_VECTOR (4 downto 0); 
      s : in STD_LOGIC; 
      z : out STD_LOGIC_VECTOR (4 downto 0)); 
end component; 

component my32to9bit is 
    Port (a : in STD_LOGIC_VECTOR (31 downto 0); 
      z : out STD_LOGIC_VECTOR (8 downto 0)); 
end component; 

component my32BitRegistersFile is 
    Port (ReadRegister1 : in STD_LOGIC_VECTOR (4 downto 0); 
      ReadRegister2 : in STD_LOGIC_VECTOR (4 downto 0); 
      WriteRegister : in STD_LOGIC_VECTOR (4 downto 0); 
      WriteData : in STD_LOGIC_VECTOR (31 downto 0); 
      ReadData1 : out STD_LOGIC_VECTOR (31 downto 0); 
      ReadData2 : out STD_LOGIC_VECTOR (31 downto 0); 
       ReadData3 : out STD_LOGIC_VECTOR (31 downto 0); 
      RegWrite : in STD_LOGIC; 
       clk : in STD_LOGIC; 
      Reset : in STD_LOGIC); 
end component; 

component myControlUnit is 
    Port (A : in STD_LOGIC_VECTOR (5 downto 0); 
      RegDst : out STD_LOGIC; 
      ALUSrc : out STD_LOGIC; 
      MemtoReg : out STD_LOGIC; 
      RegWrite : out STD_LOGIC; 
      MemRead : out STD_LOGIC; 
      MemWrite : out STD_LOGIC; 
      ALUop1 : out STD_LOGIC; 
      SinCos : out STD_LOGIC; 
      FI : out STD_LOGIC); 
end component; 

component my16to32bit is 
    Port (a : in STD_LOGIC_VECTOR (31 downto 0); 
      z : out STD_LOGIC_VECTOR (31 downto 0)); 
end component; 


component myALUControl is 
    Port (a : in STD_LOGIC_VECTOR (2 downto 0); 
      s : in STD_LOGIC; 
      op1 : out STD_LOGIC; 
      op2 : out STD_LOGIC; 
      bin : out STD_LOGIC); 
end component; 

component myALU_32bit is 
    Port (a : in STD_LOGIC_VECTOR (31 downto 0); 
      b : in STD_LOGIC_VECTOR (31 downto 0); 
      bin : in STD_LOGIC; 
      cin : in STD_LOGIC; 
      op1 : in STD_LOGIC; 
      op2 : in STD_LOGIC; 
      cout : out STD_LOGIC; 
      z : out STD_LOGIC_VECTOR (31 downto 0)); 
end component; 

component my_SinCos is 
    Port (I1 : in STD_LOGIC_VECTOR (8 downto 0); 
      s : in STD_LOGIC_VECTOR (1 downto 0); 
       e : out STD_LOGIC; 
      O : out STD_LOGIC_VECTOR (31 downto 0)); 

end component; 

component DataRAM is 
    Port (DataAddress : in STD_LOGIC_VECTOR (9 downto 0); 
      clk : in STD_LOGIC; 
      readData : in STD_LOGIC; 
      writeData : in STD_LOGIC; 
      DataIn : in STD_LOGIC_VECTOR (31 downto 0); 
      DataOut : out STD_LOGIC_VECTOR (31 downto 0)); 
end component; 

component my_32bitMUX is 
    Port (a : in STD_LOGIC_VECTOR (31 downto 0); 
      b : in STD_LOGIC_VECTOR (31 downto 0); 
      s : in STD_LOGIC; 
      z : out STD_LOGIC_VECTOR (31 downto 0)); 
end component; 

signal S2, S4, S5, S6, S7, S9 , S10 , S11, S12, S13, S14, S15, S16, S17 : STD_LOGIC_VECTOR(31 downto 0); 
signal S0, S1:STD_LOGIC_VECTOR (9 downto 0); 
signal S3:STD_LOGIC_VECTOR (4 downto 0); 
signal S8:STD_LOGIC_VECTOR (8 downto 0); 
signal SC:STD_LOGIC_VECTOR (8 downto 0); 
signal SA :STD_LOGIC_VECTOR (2 downto 0); 
signal S18:STD_LOGIC; 
begin 
U0: myPCRegister port map(PC_INPUT=>S1, PC_OUTPUT=>S0, clk=>clk, RESET=>reset); 
U1: my_10bitAdder port map (a=>S0, b=>'1', cin=>'0', z=>S1); 
U2: InstructionsROM port map(InstructionAddress=>S0 , Instruction=> S2); 
U3: my_5bitMUX port map(a=> S2(15 downto 11), b=>S2(20 downto 16), s=>SC(0), z=>S3); 
U4: my32BitRegistersFile port map(ReadRegister1=>S2(25 downto 21), ReadRegister2=>S2(20 downto 16), WriteRegister=>S3, WriteData=>S17, ReadData1=>S5, ReadData2=>S6, RegWrite=>SC(3), clk=>clk, Reset=>reset); 
U5: myControlUnit port map(A=>S2(31 downto 26),RegDst=>SC(0), ALUSrc=>SC(1), MemtoReg=>SC(2), RegWrite=>SC(3), MemRead=>SC(4), MemWrite=>SC(5), ALUop1=>SC(6), SinCos=>SC(7), FI=>SC(8)); 
U6: my16to32bit port map(a=>S2, z=>S4); 
U7: myALUControl port map(a=>S2(2 downto 0), s=>SC(6),bin=>SA(0), op1=>SA(1), op2=>SA(2)); 
U8: my_32bitMUX port map(a=>S4, b=>S6, s=>SC(1), z=>S10); 
U9: my_32bitMUX port map(a=>S11, b=>S5, s=>SC(8), z=>S9); 
U10: myALU_32bit port map(a=>S9, b=>S10, cin=>'0', bin=>SA(0), op1=>SA(1), op2=>SA(2), z=>S12); 
U11: my_32bitMUX port map(a=> S5, b=>S12, s=>SC(8), z=>S7); 
U12: my32to9bit port map(a=>S7, z=>S8); 
U13: my_SinCos port map(I1=>S8, s=>S2(31 downto 30), e=>S18, O=>S11); 
U14: DataRAM port map(DataAddress=>S2(9 downto 0), clk=>clk, readData=>SC(4), writeData=>SC(5), DataIn=>S6, DataOut=>S14); 
U15: my_32bitMUX port map(a=>S12, b=>S11, s=>SC(8), z=>S13); 
U16: my_32bitMUX port map(a=>S14, b=>S12, s=>SC(2), z=>S15); 
U17: my_32bitMUX port map(a=>S11, b=>S15, s=>SC(7), z=>S16); 
U18: my_32bitMUX port map(a=>S11, b=>S16, s=>S18, z=>S17); 
instruction<=S2; 
regA<=S9; 
regB<=S10; 
ALUout<=S12;   
writeReg<=S3; 
Opcode<=S2(31 downto 26); 
SinCos<= S11; 
DataOUT<=S14; 
WriteData<=S17; 
ReadDATA1<= S5; 
ReadDATA2 <=S6; 
end Behavioral; 

DATARAM

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

---- Uncomment the following library declaration if instantiating 
---- any Xilinx primitives in this code. 
--library UNISIM; 
--use UNISIM.VComponents.all; 

entity DataRAM is 
    Port (DataAddress : in STD_LOGIC_VECTOR (9 downto 0); 
      clk : in STD_LOGIC; 
      readData : in STD_LOGIC; 
      writeData : in STD_LOGIC; 
      DataIn : in STD_LOGIC_VECTOR (31 downto 0); 
      DataOut : out STD_LOGIC_VECTOR (31 downto 0)); 
end DataRAM; 

architecture Behavioral of DataRAM is 

-- Define a new type with the name RAM_Array of 8 bits 
type RAM_Array is array (0 to 1023) 
    of std_logic_vector(7 downto 0); 
-- Set some initial values in RAM for Testing 
signal RAMContent: RAM_Array := (
    0 => X"0A", 1 => X"00", 2 => X"00", 3 => X"00", 
    4 => X"05", 5 => X"00", 6 => X"00", 7 => X"00", 
    8 => X"2C", 9 => X"01", 10 => X"00", 11 => X"00", 
    12 => X"00", 13 => X"00", 14 => X"00", 15 => X"00", 

    others => X"00"); 

begin 
    -- This process is called when we READ from RAM 
    p1: process (readData, DataAddress) 
    begin 
     if readData = '1' then 
     DataOut(7 downto 0) <= RAMContent(conv_integer(DataAddress)); 
     DataOut(15 downto 8) <= RAMContent(conv_integer(DataAddress+1)); 
     DataOut(23 downto 16) <= RAMContent(conv_integer(DataAddress+2)); 
     DataOut(31 downto 24) <= RAMContent(conv_integer(DataAddress+3)); 
     else 
      DataOut <= (DataOut'range => 'Z'); 
     end if; 
    end process; 


    -- This process is called when we WRITE into RAM 
    p2: process (clk, writeData) 
    begin 
     if (clk'event and clk = '1') then 
      if writeData ='1' then 
       RAMContent(conv_integer(DataAddress)) <= DataIn(7 downto 0); 
       RAMContent(conv_integer(DataAddress+1)) <= DataIn(15 downto 8); 
       RAMContent(conv_integer(DataAddress+2)) <= DataIn(23 downto 16); 
       RAMContent(conv_integer(DataAddress+3)) <= DataIn(31 downto 24); 
      end if; 
     end if; 
    end process; 
end Behavioral; 

취급 ROM

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

---- Uncomment the following library declaration if instantiating 
---- any Xilinx primitives in this code. 
--library UNISIM; 
--use UNISIM.VComponents.all; 

entity InstructionsROM is 
    Port (InstructionAddress : in STD_LOGIC_VECTOR (9 downto 0); 
      Instruction : out STD_LOGIC_VECTOR (31 downto 0)); 
end InstructionsROM; 

architecture Behavioral of InstructionsROM is 
-- Define a new type with the name ROM_Array of 32 bits 
type ROM_Array is array (0 to 1024) 
    of std_logic_vector(31 downto 0); 

-- The data here should be replaced with the intructions in HEX 
constant ROMContent: ROM_Array := (
        X"8C000000", 

        X"8C810000", 
        X"00201822", 
        X"00201824", 
        X"00201825", 
        X"8D000000", 
        X"8D810000", 
        X"BC03000A", 
        X"FC03000A", 
        X"3C03000A", 
        X"7C03000A", 

    others => X"00000000"); 
begin 

    Instruction <= ROMContent(conv_integer(InstructionAddress)); 

end Behavioral; 

DataRam 및 instructionrom이 ... 우리 그냥 값을 변경할 준비가 우리에게 주어졌다

(우리가 수행 할 작업을 지시에 따라 다름)

Answer 1

코드에 심각한 문제가 있습니다.

,

• P1 : cout
• U4를 연결되지 않은 : readdata3는
• U10 연결되지 않습니다 cout이
• U14
연결되지 않습니다 component이 my_32bitMUX_937286가 선언되지 않은 프로세스 감도 목록 RAMContent
• U1이 포함되어야한다 . 컴파일 오류가 발생합니다

처음 네 가지 문제는 시뮬레이터에서 경고없이 문제를 일으킬 수 있습니다. 마지막은 오류이며 일반적으로 시뮬레이터에서 오류를 발생시키고 시뮬레이션을 시작하지 않습니다.