Verilog에서 여러 배열을 하나의 배열로 결합하는 방법은 무엇입니까? 여기

Question

내 코드입니다 :

module MIPS_Processor(); 
    reg [7:0] mem [0:4095];  // 4K memory cells that are 8 bits wide 
    reg [7:0] code[0:1023];  // 1K memory cells that are 8 bits wide 
    reg [31:0] registers[0:31]; // 32 registers that are 32 bits wide 
    reg [31:0] PC;    // The program counter 

    initial 
     begin 
      PC = 0; 
     end 

    always 
     begin 
      // 1. Fetch an instruction from memory 
      bit [31:0] instruction = {{code[PC * 8 + 7:PC * 8 + 0]}, 
            {code[(PC + 1) * 8 + 7:(PC + 1) * 8 + 0]}, 
            {code[(PC + 2) * 8 + 7:(PC + 2) * 8 + 0]}, 
            {code[(PC + 3) * 8 + 7:(PC + 3) * 8 + 0]}}; 

      // 2. Increment the program counter register (by the instruction length) 
      PC = PC + 4; 

      // Rest of the code 

    end 
endmodule 

나는 코드에서 명령을 가져 오기 위해 하나 개의 배열에 4 개 배열을 결합 할 수있는 방법

? 위의 코드는 컴파일되지 않습니다!

---

편집 : 그것은 컴파일되지 않습니다 여전히

bit [31:0] instruction = { 
        code[PC + 0], 
        code[PC + 1], 
        code[PC + 2], 
        code[PC + 3] 
}; 

:

@toolic이 어떤 제안에 코드를 변경 한 후

을 사용하여 자일링스 :

========================================================================= 
*       HDL Compilation        * 
========================================================================= 
Compiling verilog file "MIPS_Processor.v" in library work 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 expecting ']', found ':' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 unexpected token: '=' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 unexpected token: '{' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 40 expecting '.', found ',' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 41 expecting '.', found ',' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 42 expecting '.', found ',' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 44 expecting '.', found '}' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 unexpected token: '=' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 unexpected token: 'PC' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 expecting 'end', found '+' 
Module <MIPS_Processor> compiled 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 expecting 'endmodule', found '4' 
Analysis of file <"MIPS_Processor.prj"> failed. 
--> 

Total memory usage is 274336 kilobytes 

Number of errors : 11 ( 0 filtered) 
Number of warnings : 0 ( 0 filtered) 
Number of infos : 0 ( 0 filtered) 


Process "Synthesize - XST" failed 

하는 Verilogger 극단적 사용 :

Answer 1

는 code 메모리의 연속하는 4 바이트로부터 명령 워드 형성하려면 제쳐두고로서

// 1. Fetch an instruction from memory 
bit [31:0] instruction = { 
         code[PC + 0], 
         code[PC + 1], 
         code[PC + 2], 
         code[PC + 3] 
};