5 초 VHDL 타이머

Question

저는 50MHz 클럭을 FPGA에서 사용하고 5 초 타이머를 만들려고합니다. cnt_t에 도달하면 5 x 50MHz (x "0EE6B280"-> 250,000,000)가됩니다. 그런 다음 time_tick_32를 1로 설정하고 cnt_t를 < = x "00000000";으로 만듭니다. 아래의 코드는 1

signal cnt_t : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000"; 
signal time_tick : STD_LOGIC:= '0' ; 
signal time_tick_32 : STD_LOGIC_VECTOR(31 DOWNTO 0):= x"00000000"; 


process (clk_50) IS 
    begin 
     if falling_edge(clk_50) then 
     cnt_t <= cnt_t + '1'; 
     end if; 
    if (cnt_t = x"0EE6B280") then --if 5 seconds 
     time_tick <= '1'; 
     cnt_t <= x"00000000"; 
     time_tick_32(0)<=time_tick; 
    else 
     time_tick <= '0'; 
     time_tick_32(0)<=time_tick; 
    end if; 

end process; 

Answer 1

한번에 얻을 수 없다 time_tick_32 작동하지 않았다 :이 언어에 대한

signal cnt_t : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000"; 
signal time_tick : STD_LOGIC:= '0' ; 
signal time_tick_32 : STD_LOGIC_VECTOR(31 DOWNTO 0):= x"00000000"; 


-- I assume you begin your architecture somewhere 
-- Can make the following a concurrent statement 
-- (unless it is some kind of shift reg assigned in a diff process... 
-- then you will get multiple driver issues) 
time_tick_32(0) <= time_tick; 

process (clk_50) IS 
begin 
    if rising_edge(clk_50) then -- Changed to rising_edge; 
           -- Any particular reason you are using falling_edge? 
     if (cnt_t = x"0EE6B280") then --if 5 seconds 
      time_tick <= '1'; 
      cnt_t <= x"00000000"; 
     else 
      time_tick <= '0'; 
      cnt_t <= cnt_t + '1'; 
     end if; 
    end if; 
end process;